[PATCH] D93750: [RISCV] Frame handling for RISC-V V extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

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This patch proposes how to deal with RISC-V vector frame objects. The layout of RISC-V vector frame will look like

  |---------------------------------|
  | RVV incoming arguments          |
  |---------------------------------| previous frame
  | scalar incoming arguments       |
  |---------------------------------| <- start of frame (fp)
  | scalar callee-saved registers   |
  |---------------------------------|
  | scalar local variables          |
  |---------------------------------|
  | addresses of RVV objects (*)    | current frame
  |---------------------------------|
  | RVV local variables             |
  |---------------------------------|
  | RVV outgoing arguments          |
  |---------------------------------|
  | scalar outgoing arguments       |
  |---------------------------------| <- end of frame (sp)

We will reserve stack space for RISC-V vector frame objects and store their base addresses in “addresses of RVV objects” area. The benefits of this way is we have no need to calculate the addresses of RVV objects repeatedly. There is no easy way to get the addresses of the RISC-V vector objects in V instructions. We need to read out VLENB and multiple VLENB with LMUL to know the size of vector objects. Then we need to subtract or add the size from the stack pointer. If there are multiple vector objects in the frame, we need to subtract or add the accumulated size from the stack pointer. If we store the base addresses in the frame first, we only need to load the base address from the stack frame and access the vector object directly.

Spilling for RISC-V V extension will be another patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93750

Files:
  llvm/include/llvm/CodeGen/MIRYamlMapping.h
  llvm/include/llvm/CodeGen/MachineFrameInfo.h
  llvm/include/llvm/CodeGen/TargetFrameLowering.h
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args-with-scalar.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll

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