[PATCH] D91053: [PowerPC] Lump the constants to save one addis for each constant access

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

In D91053#2467539 <https://reviews.llvm.org/D91053#2467539>, @nemanjai wrote:

> In D91053#2467200 <https://reviews.llvm.org/D91053#2467200>, @steven.zhang wrote:
>
>> The test you are looking for is llvm/test/CodeGen/PowerPC/constant-pool.ll in fact.
>
> Not quite. There seems to only be float/double/double double/vector and only for P9 <https://reviews.llvm.org/P9>/P10 <https://reviews.llvm.org/P10>. What happens with:
>
> 1. enough constants that the load is widened

IIUC, we won't have any impact on the optimization of DAG as what we changed is on the step that legalize the constant pool, which is done after DAGCombine. Anyway, I will add this test point with your test.

> 2. what happens with `-mcpu=pwr8` to see the impact of this when there are no D-Form loads for vectors

It is done.

> Also, the test case with multiple constants should show the constant pool (including alignment).

Good suggestion. It is done.

> A simple example exhibiting this behaviour would be something like
>
>   void test(double *ArrD, unsigned short *ArrS, float *ArrF) {
>   // Ensure that these are still widened to 8b + 4b + 2b
>     ArrS[0] = 12;
>     ArrS[1] = 44;
>     ArrS[2] = 8;
>     ArrS[3] = 98;
>     ArrS[4] = 271;
>     ArrS[5] = 888;
>     ArrS[6] = 99;
>   
>   // These are not vectorized, check 4b alignment
>     ArrF[0] += 999.88f;
>     ArrF[1] += 861.15f;
>   
>   // These are vectorized, check 16b alignment
>     ArrD[0] = 342.2312;
>     ArrD[1] = 664435.988;
>     ArrD[3] = 12.222;
>     ArrD[4] = 12.222;
>   
>   // Check 8b alignment
>     ArrD[5] += 2377.797889;
>   }

Thank for for the test. I have added into constant-pool.ll


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