[PATCH] D55301: RegAlloc: Allow targets to split register allocation

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 313463.
arsenm added a comment.
Herald added subscribers: wenlei, hiraditya.
Herald added a project: LLVM.

Rebase, fix AGPR handling


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55301/new/

https://reviews.llvm.org/D55301

Files:
  llvm/include/llvm/CodeGen/Passes.h
  llvm/include/llvm/CodeGen/RegAllocCommon.h
  llvm/include/llvm/CodeGen/RegAllocRegistry.h
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/lib/CodeGen/RegAllocBase.cpp
  llvm/lib/CodeGen/RegAllocBase.h
  llvm/lib/CodeGen/RegAllocBasic.cpp
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
  llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
  llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
  llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir

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