[PATCH] D93272: [InstCombine] Add checking of i1 types when converting select instructions into zext/sext instructions

[Congzhe Cao via Phabricator via llvm-commits]

congzhe updated this revision to Diff 313147.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93272/new/

https://reviews.llvm.org/D93272

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp


Index: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -2606,7 +2606,10 @@
   // select i1 %c, <2 x i8> <1, 1>, <2 x i8> <0, 0>
   // because that may need 3 instructions to splat the condition value:
   // extend, insertelement, shufflevector.
-  if (SelType->isIntOrIntVectorTy() &&
+  //
+  // Do not handle i1 TrueVal and FalseVal otherwise would result in
+  // zext/sext i1 to i1.
+  if (SelType->isIntOrIntVectorTy() && !SelType->isIntOrIntVectorTy(1) &&
       CondVal->getType()->isVectorTy() == SelType->isVectorTy()) {
     // select C, 1, 0 -> zext C to int
     if (match(TrueVal, m_One()) && match(FalseVal, m_Zero()))


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D93272.313147.patch
Type: text/x-patch
Size: 826 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201221/adc44c7b/attachment.bin>