[PATCH] D93608: [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1754
 defm PseudoVSLIDEDOWN  : VPseudoTernaryV_VX_VI<uimm5>;
+defm PseudoVSLIDE1UP   : VPseudoBinaryV_VX</*IsFloat*/0>;
+defm PseudoVSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/0>;
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Doesn't slide1up need an earlyclobber?


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Comment at: llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll:12
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfslide1up.vf {{v[0-9]+}}, {{v[0-9]+}}, ft0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
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It would be nice if we used the update_llc_test_checks.py script to generate these tests so we could see whether the source and destination register were the same or not.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93608/new/

https://reviews.llvm.org/D93608