[PATCH] D93537: [AArch64] Fix inline assembly parsing crash

[David Sherwood via Phabricator via llvm-commits]

david-arm updated this revision to Diff 313103.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93537/new/

https://reviews.llvm.org/D93537

Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll


Index: llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
===================================================================
--- llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
+++ llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
@@ -6,6 +6,7 @@
 ; CHECK: error: couldn't allocate input reg for constraint 'Upa'
 ; CHECK: error: couldn't allocate input reg for constraint 'r'
 ; CHECK: error: couldn't allocate output register for constraint 'w'
+; CHECK: error: unknown token in expression
 
 define <vscale x 16 x i1> @foo1(i32 *%in) {
 entry:
@@ -27,3 +28,11 @@
   %1 = call <vscale x 16 x i1> asm sideeffect "mov $0.b, $1.b \0A", "=&w,w"(<vscale x 16 x i1> %0)
   ret <vscale x 16 x i1> %1
 }
+
+define half @foo4(<vscale x 16 x i1> *%inp, <vscale x 8 x half> *%inv) {
+entry:
+  %0 = load <vscale x 16 x i1>, <vscale x 16 x i1>* %inp, align 2
+  %1 = load <vscale x 8 x half>, <vscale x 8 x half>* %inv, align 16
+  %2 = call half asm "fminv ${0:h}, $1, $2.h", "=r, at 3Upl,w"(<vscale x 16 x i1> %0, <vscale x 8 x half> %1)
+  ret half %2
+}
Index: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -647,7 +647,8 @@
   const TargetRegisterInfo *RI = STI->getRegisterInfo();
   Register Reg = MO.getReg();
   unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
-  assert(RI->regsOverlap(RegToPrint, Reg));
+  if (!RI->regsOverlap(RegToPrint, Reg))
+    return true;
   O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
   return false;
 }


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