[PATCH] D93370: [PowerPC][NFC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In D93370#2461971 <https://reviews.llvm.org/D93370#2461971>, @shchenz wrote:

> So for the new infra, I am thinking should we avoid this redundant logic? I still see redundant checks/flags collects for one load/store instruction. We first check `SelectDSForm` and then check `SelectXForm` and then `SelectForceXForm` according to the order in td files. In each `SelectXXXForm()`, we will collect the flags once. There should also be some redundant logics?
>
> Can we select the address mode not starting from td files? Instead, we start the selection from cpp file for IR level load? For example in function `PPCDAGToDAGISel::Select()`, change case ISD::LOAD and inside the case, we call `SelectOptimalAddrMode` and then select the PPC instruction directly in cpp files.

I think this may be an interesting follow-up to optimize this slightly. However, I would imagine we would do this in `PreprocessISelDAG()`. Namely, we can replace `ISD::LOAD` with something like `PPCISD::LOAD_W_ADDRMODE` (and similarly for the stores). That way we can still specify more complex patterns in .td files rather than reimplementing everything in C++ code. Namely, we can still add things like:

  def : Pat<(f128 (sint_to_fp (i64 (load xaddrX4:$src)))),
            (f128 (XSCVSDQP (LXSDX xaddrX4:$src)))>;

except it would be something like:

  def : Pat<(f128 (sint_to_fp (i64 (PPCloadWAddForm DSForm:$src)))),
            (f128 (XSCVSDQP (LXSD DSForm:$src)))>;

However, considering the number of loads/stores in a typical DAG and how quickly these flags, etc. can be computed, this isn't a huge compile time improvement.


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