[PATCH] D93624: [RISCV] Fix rounding mode in lowering of float operations

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added a comment.

In D93624#2465776 <https://reviews.llvm.org/D93624#2465776>, @jrtc27 wrote:

> Doesn't this render `fesetround` useless?

No. `fesetround` sets dynamic rounding mode (register frm), which may be any mode. However in the case of non-default rounding mode (all other than RNE), floating operations must be represented by constrained intrinsics, for example `llvm.experimental.constrained.fadd` should be used instead of `fadd`.



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Comment at: llvm/test/CodeGen/RISCV/double-arith.ll:40
+; RV32IFDIS-LABEL: <fadd_d>:
+; RV32IFDIS:      fadd.d ft0, ft1, ft0, rne
   %1 = fadd double %a, %b
----------------
jrtc27 wrote:
> I don't understand this. Either you're changing CodeGen which should mean the assembly changes or you're changing the assembler which should instead be tested in the MC tests. You should almost never need to disassemble during a CodeGen test.
I see. Changed assertions in the produced assembler.


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  https://reviews.llvm.org/D93624/new/

https://reviews.llvm.org/D93624