[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

Mon Dec 21 04:32:06 PST 2020

frasercrmck marked 4 inline comments as done.
frasercrmck added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1399
+    // accidentally sign-extend the 32-bit halves to the e64 SEW:
+    //   vmv.v.x vX, hi
+    //   vsll.vx vX, vX, /*32*/
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craig.topper wrote:
> Is it possible to build this sequence from LowerSPLAT_VECTOR using ISD::SHL, ISD::SRL, ISD::OR, RISCVISD::SPLAT_VECTOR_I64, etc? That's probably better than emitting a large sequence in the isel table.
Agreed, especially since I don't think we'll ever need to do special codegen for SPLAT_VECTOR_I64_PAIR so we might as well expand it early. I've now removed it and expand it in `LowerSPLAT_VECTOR`.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312