[PATCH] D91255: [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup))

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11586
+static EVT calculatePreExtendType(SDValue Extend, SelectionDAG &DAG) {
+  const SDValue &ExtOperand = Extend.getOperand(0);
+
----------------
const SDValue &ExtOperand -> SDValue ExtOperand

Its also only used in one place and needn't get a variable.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11595
+  case ISD::SIGN_EXTEND_INREG: {
+    const SDValue &TypeOperand = Extend.getOperand(1);
+    VTSDNode *TypeNode = dyn_cast<VTSDNode>(TypeOperand);
----------------
const SDValue &TypeOperand -> SDValue TypeOperand


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11633
+
+  SDValue InsertVectorElt = VectorShuffle.getOperand(0);
+  SDValue Extend = InsertVectorElt.getOperand(1);
----------------
This doesn't seem to be checking that the shuffle/insert are actually a splat.

There is an isSplatValue method that could help, depending on if it's really checking what this wants to check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91255/new/

https://reviews.llvm.org/D91255