[PATCH] D93606: [SVE] Lower vector BITREVERSE and BSWAP operations.

[Paul Walker via Phabricator via llvm-commits]

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These operations are lowered to RBIT and REVB instructions
respectively.  In the case of fixed-length support using SVE we
also lower BITREVERSE operating on NEON sized vectors as this
results in fewer instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93606

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
  llvm/test/CodeGen/AArch64/sve-rev.ll

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