[PATCH] D93578: [RISCV] Upgrade RISC-V V extension MC to v1.0-08a0b46.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2310
-        Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM ||
-        Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM ||
-        Opcode == RISCV::VMERGE_VXM)
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craig.topper wrote:
> HsiangKai wrote:
> > craig.topper wrote:
> > > Why is this being dropped? This was a bug fix I just earlier this week. I don't think vmerge can ever V0 as a destination and the parser previously crashed on it.
> > I could not find the description that the destination of vmerge could not be V0 as I scanned the V specification. So, I remove it. Maybe I misread the specification. We should confirm it first.
> It should be covered by this "The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., comparisons) or the scalar result of a reduction. Otherwise, an illegal instruction exception is raised.  
> This constraint supports restart with a non-zero vstart value"
Got it. Thanks. I will revert it.


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  https://reviews.llvm.org/D93578/new/

https://reviews.llvm.org/D93578