[PATCH] D88386: [MIR][M68K] (Patch 2/8): Changes on Target-independent MIR part

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:947-955
+  /// Allow targets to tell MachineVerifier whether specific register
+  /// MachineOperand can be pc-relative.
+  /// PC-relative addressing modes in many CISC architectures contain
+  /// (non-pc) register as offset or scaling values. Which inherently
+  /// tags the corresponding MachineOperand with OPERAND_PCREL.
+  ///
+  /// @param MO  The MachineOperand in question. MO.isReg() should always
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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:956
+  /// @return Whether this operand is allowed to be pc-relative.
+  virtual bool isRegisterOperandPCRel(const MachineOperand &MO) const {
+    return false;
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Current name doesn't make sense; the operand is PC-relative, but the question is whether that's a legal thing to have constructed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88386/new/

https://reviews.llvm.org/D88386