[PATCH] D93584: [RISCV] Define vector vfwmul intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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Define vector vfwmul intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93584

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll

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