[PATCH] D93571: [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: efriedma.
Herald added subscribers: danielkiss, lebedev.ri, gbedwell, kristof.beyls.
Herald added a reviewer: andreadb.
Herald added a reviewer: lebedev.ri.
craig.topper requested review of this revision.
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These properties aren't additive. They are closer to ReadOnly and
WriteOnly. The default is ReadWrite. ReadMem cancels the write property and
WriteMem cancels the read property. Combining them leaves neither.

This patch checks that when we process WriteMem, the Mod flag is
still set. And for ReadMem we check that the Fef flag set still set.

I've update 2 target intrinsics that were combining these properties.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93571

Files:
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/test/tools/llvm-mca/X86/Atom/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/BtVer2/stmxcsr-ldmxcsr.s
  llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Haswell/stmxcsr-ldmxcsr.s
  llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Znver1/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/Znver1/resources-sse1.s
  llvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
  llvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
  llvm/utils/TableGen/CodeGenTarget.cpp

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