[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:85
   // scalar is split into two i32 operands: low and high halves
   SPLAT_VECTOR_I64_PAIR,
 };
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Is there a different patch that adds SPLAT_VECTOR_I64_PAIR?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:636
+let Complexity = 1 in
+def SplatPat       : ComplexPattern<vAny, 1, "SelectVSplat", [splat_vector, rv32_splat_i64]>;
+def SplatPat_simm5 : ComplexPattern<vAny, 1, "SelectVSplat_simm5", [splat_vector, rv32_splat_i64]>;
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I don't think you want anything in the square brackets. That autogenerates a pattern for splat_vector/rv32_splat_i64 as the root node for the isel match. I guess your vmv.v.v pattern is getting priority so its not causing a problem?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312