[PATCH] D93551: AMDGPU: Add spilled CSR SGPRs to entry block live ins

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kerbowa, scott.linder.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, qcolombet.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

https://reviews.llvm.org/D93551

Files:
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir


Index: llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx906 -run-pass=si-lower-sgpr-spills,prologepilog -o - %s | FileCheck %s
+
+# Make sure the modified CSR VGPRs are added as live-in to the entry
+# block.
+
+---
+name: def_csr_sgpr
+tracksRegLiveness: true
+machineFunctionInfo:
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
+  stackPtrOffsetReg: $sgpr32
+body: |
+  ; CHECK-LABEL: name: def_csr_sgpr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $sgpr42, $sgpr43, $sgpr46, $sgpr47, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr42, 0, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr43, 1, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr46, 2, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr47, 3, $vgpr0
+  ; CHECK:   S_NOP 0
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $vgpr0
+  ; CHECK:   $sgpr42 = S_MOV_B32 0
+  ; CHECK:   $sgpr43 = S_MOV_B32 1
+  ; CHECK:   $sgpr46_sgpr47 = S_MOV_B64 2
+  bb.0:
+    S_NOP 0
+
+  bb.1:
+    $sgpr42 = S_MOV_B32 0
+    $sgpr43 = S_MOV_B32 1
+    $sgpr46_sgpr47 = S_MOV_B64 2
+...
+
Index: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -185,6 +185,16 @@
   }
 }
 
+// TODO: To support shrink wrapping, this would need to copy
+// PrologEpilogInserter's updateLiveness.
+static void updateLiveness(MachineFunction &MF, ArrayRef<CalleeSavedInfo> CSI) {
+  MachineBasicBlock &EntryBB = MF.front();
+
+  for (const CalleeSavedInfo &CSIReg : CSI)
+    EntryBB.addLiveIn(CSIReg.getReg());
+  EntryBB.sortUniqueLiveIns();
+}
+
 bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const Function &F = MF.getFunction();
@@ -222,6 +232,10 @@
       for (MachineBasicBlock *SaveBlock : SaveBlocks)
         insertCSRSaves(*SaveBlock, CSI, LIS);
 
+      // Add live ins to save blocks.
+      assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
+      updateLiveness(MF, CSI);
+
       for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
         insertCSRRestores(*RestoreBlock, CSI, LIS);
       return true;


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