[PATCH] D93364: [RISCV] Load/Store vector mask types.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D93364#2462242 <https://reviews.llvm.org/D93364#2462242>, @HsiangKai wrote:

> D93368 <https://reviews.llvm.org/D93368> will depend on this commit. For example, there are four vector arguments in the masked version of vmseq, i.e., maskedoff, varg0, varg1, mask. When LMUL = 4, we could pass the arguments varg0 and varg1 through vector registers. The first mask type argument will be put in v0. The second mask type argument, i.e., mask, will pass through stack. The address will be stored in the GPR. We need to load the mask value from the stack. Vector argument passing is another issue. We could create another patch for it.

Are you saying the tests in D93368 <https://reviews.llvm.org/D93368> don't pass without this commit?


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  https://reviews.llvm.org/D93364/new/

https://reviews.llvm.org/D93364