[PATCH] D93370: [PowerPC][NFC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns.

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

I should have said this in my first comments. I like this refactor. I just want to make sure I understand this refactoring more clear^_^. Thanks for your detailed explanation. @nemanjai

For legacy infra, I have one pain for the matching efficiency. When we match a worst-case in td files, we will 
1: first check dform candidate and in dform candidate handling function `SelectAddressRegImm`, we check xform candidate. If it fails:
2: check xform candidate and in xform candidate handling function `SelectAddressRegReg`, we will check dform candidate. If it fails:
3: check xform only candidate and in xform only candidate handling function `SelectAddressRegRegOnly`, we will get the desired hardware instructions.

I think there must be logic redundant. We check again and again for the load/store address mode.

So for the new infra, I am thinking should we avoid this redundant logic? I still see redundant checks/flags collects for one load/store instruction. We first check `SelectDSForm` and then check `SelectXForm` and then `SelectForceXForm` according to the order in td files. In each `SelectXXXForm()`, we will collect the flags once. There should also be some redundant logics?

Can we select the address mode not starting from td files? Instead, we start the selection from cpp file for IR level load? For example in function `PPCDAGToDAGISel::Select()`, change case ISD::LOAD and inside the case, we call `SelectOptimalAddrMode` and then select the PPC instruction directly in cpp files.


Repository:
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https://reviews.llvm.org/D93370