[PATCH] D93366: [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1076
+      unsigned ExtendOp = II->ExtendedOperand + 1;
+      if (ExtendOp) {
+        assert(ExtendOp < Op.getNumOperands());
----------------
I think this if needs to be based on II->ExtendedOperand before adding 1 to it. Otherwise its guaranteed to always be true.


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  https://reviews.llvm.org/D93366/new/

https://reviews.llvm.org/D93366