[PATCH] D93365: [RISCV] Add intrinsics for vmv.x.s and vmv.s.x
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 17 01:29:30 PST 2020
craig.topper updated this revision to Diff 312403.
craig.topper added a comment.
Herald added a subscriber: jrtc27.
Add tied register constraint. Remove unnecessary type from intrinsic names in tests.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93365/new/
https://reviews.llvm.org/D93365
Files:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
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