[PATCH] D93426: [RISCV] Add intrinsics for vfmv.f.s and vfmv.s.f

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1276
+  def : Pat<(fvti.Scalar (int_riscv_vfmv_f_s (fvti.Vector fvti.RegClass:$rs2))),
+             // Floating point instructions with a scalar result will always
+             // generate the result in a register of class FPR32. When dealing
----------------
Is this the opposite of `ToFPR32`? Should we thus define `FromFPR32`? At any rate we can presumably `defvar inst = !cast<Instruction>...` to reduce code duplication.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93426/new/

https://reviews.llvm.org/D93426