[PATCH] D93365: [RISCV] Add intrinsics for vmv.x.s and vmv.s.x

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1135
+                                             []>, RISCVVPseudo;
+      let VLIndex = 3, SEWIndex = 4, BaseInstr = VMV_S_X in
+      def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd),
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Do we need to add a constraint "$rd = $rs1"?


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  https://reviews.llvm.org/D93365/new/

https://reviews.llvm.org/D93365