[PATCH] D90349: [DAGCombiner] Improve shift by select of constant
    Qing Shan Zhang via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Wed Dec 16 23:52:09 PST 2020
    
    
  
steven.zhang added inline comments.
================
Comment at: llvm/test/CodeGen/PowerPC/select_const.ll:632
+; NO_ISEL-NEXT:    addi 3, 4, 0
+; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 2, i8 3
----------------
RKSimon wrote:
> lebedev.ri wrote:
> > RKSimon wrote:
> > > laytonio wrote:
> > > > RKSimon wrote:
> > > > > any ideas on these regressions?
> > > > > any ideas on these regressions?
> > > > 
> > > > Forgive me, I'm not very familiar with PowerPC, but is this actually worse? It now looks just like the above unaltered test for select of constants shifted by constant. If it is worse, should we change that as well?
> > > @nemanjai how much of an issue is this?
> > @nemanjai ping
> @amyk Any comments?
It looks good to me as before the change, clrlwi,  subfic and slw are chained together, while the new one only chain two instructions.(andi. and iselgt) And they didn't have too much latency difference AFAIK. But please correct me if I miss something here.
Repository:
  rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90349/new/
https://reviews.llvm.org/D90349
    
    
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