[PATCH] D93380: [RISCV] Define vector mul/div/rem intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdd5281e7cce5: [RISCV] Define vector mul/div/rem intrinsics. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93380/new/

https://reviews.llvm.org/D93380

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll