[PATCH] D92156: [PowerPC] Add support for "tlbiel" with two arguments

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers added a comment.

> Regarding to usage in kernel, I think it depends on which arch are you building for, if it's with -mcpu=pwr9 and above, yes, I would recommend we update the code to use 5 operands basic form.

I haven't verified yet that `-mcpu=pwr9` is being used, but it looks like the one TU that's using `tlbie` with 2 operands mixes the use of 2 and 5 operand variants without any kind of check from what I can tell.  If that's the case, we might be able to do:

  diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
  index ed161ef2b3ca..920d47866780 100644
  --- a/arch/powerpc/include/asm/ppc-opcode.h
  +++ b/arch/powerpc/include/asm/ppc-opcode.h
  @@ -362,7 +362,6 @@
   #define PPC_RAW_RFMCI                  (0x4c00004c)
   #define PPC_RAW_TLBILX(t, a, b)                (0x7c000024 | __PPC_T_TLB(t) |  __PPC_RA0(a) | __PPC_RB(b))
   #define PPC_RAW_WAIT(w)                        (0x7c00007c | __PPC_WC(w))
  -#define PPC_RAW_TLBIE(lp, a)           (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
   #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
          (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
   #define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
  @@ -554,7 +553,7 @@
   #define PPC_TLBILX_PID(a, b)   PPC_TLBILX(1, a, b)
   #define PPC_TLBILX_VA(a, b)    PPC_TLBILX(3, a, b)
   #define PPC_WAIT(w)            stringify_in_c(.long PPC_RAW_WAIT(w))
  -#define PPC_TLBIE(lp, a)       stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
  +#define PPC_TLBIE(lp, a)       stringify_in_c(.long PPC_RAW_TLBIE_5(a, lp))
   #define        PPC_TLBIE_5(rb, rs, ric, prs, r) \
                                  stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
   #define        PPC_TLBIEL(rb,rs,ric,prs,r) \
  diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c
  index 52e170bd95ae..a4e92b8ed0aa 100644
  --- a/arch/powerpc/mm/book3s64/hash_native.c
  +++ b/arch/powerpc/mm/book3s64/hash_native.c
  @@ -177,7 +177,7 @@ static inline unsigned long  ___tlbie(unsigned long vpn, int psize,
                  va |= ssize << 8;
                  sllp = get_sllp_encoding(apsize);
                  va |= sllp << 5;
  -               asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
  +               asm volatile(ASM_FTR_IFCLR("tlbie 0,%0,0,0,0", PPC_TLBIE(%1,%0), %2)
                               : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
                               : "memory");
                  break;
  @@ -196,7 +196,7 @@ static inline unsigned long  ___tlbie(unsigned long vpn, int psize,
                   */
                  va |= (vpn & 0xfe); /* AVAL */
                  va |= 1; /* L */
  -               asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
  +               asm volatile(ASM_FTR_IFCLR("tlbie 1,%0,0,0,0", PPC_TLBIE(%1,%0), %2)
                               : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
                               : "memory");
                  break;

(Though the order of operands being switched, IIUC, is confusing, so maybe best to just remove `PPC_TLBIE` and require the use of `PPC_TLBIE_5`).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92156/new/

https://reviews.llvm.org/D92156