[PATCH] D93364: [RISCV] Load/Store vector mask types.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/load-mask.ll:14
+; CHECK-NEXT:    ret
+  %a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
+  store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
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rogfer01 wrote:
> craig.topper wrote:
> > How do we ensure that the location we're loading/storing is the right size for this? The mask is (vlenb/8) * 64 * 1 bits. But the load/store size is (vlenb/8)*64*8 bits.
> I imagine we could set `vl=max(1,vlenb/(8*8)),sew=8` in this case rather than `vl=vlmax,sew=8`. We still have to load/store at least one `i8` (hence the `max`). This is what already happens when a scalar load/store of `i1` appears in IR.
> 
> However I'm not sure whether this scenario in IR will happen very often. If it doesn't then I imagine the slightly less straightforward code generation may be OK?
I forgot to account `lmul`, so I think a reasonable `vl` would be  `vl=max(1, (vlenb*lmul)/(8*8)))`


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