[PATCH] D93364: [RISCV] Load/Store vector mask types.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 16 11:49:33 PST 2020
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/load-mask.ll:14
+; CHECK-NEXT: ret
+ %a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
+ store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
----------------
How do we ensure that the location we're loading/storing is the right size for this? The mask is (vlenb/8) * 64 * 1 bits. But the load/store size is (vlenb/8)*64*8 bits.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D93364/new/
https://reviews.llvm.org/D93364
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