[PATCH] D93286: [RISCV] Define vslideup/vslidedown intrinsics and lower to V instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

The destination register group for `vslideup` cannot overlap with the source vector register group, so I think we need an extra `earlyclobber` constraint passed to those pseudos.


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https://reviews.llvm.org/D93286