[PATCH] D93380: [RISCV] Define vector mul/div/rem intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

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Define vector mul/div/rem intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93380

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll