[PATCH] D93366: [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.

[Monk Chiang via Phabricator via llvm-commits]

monkchiang created this revision.
monkchiang added reviewers: evandro, craig.topper, frasercrmck, rogfer01, Hsiang-Kai, arcbbb.
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  We work with @rogfer01 from BSC to come out this patch.
  
  Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
  Co-Authored-by: ShihPo Hung <shihpo.hung at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93366

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll

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