[PATCH] D92296: [AARCH64] Improve accumulator forwarding for Cortex-A57 model

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA57.td:379
 // ASIMD multiply, D-form
-def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
+def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
 // ASIMD multiply, Q-form
----------------
Do PMUL and sqdmulh have this forwarding? Same for other instructions like SQDMLAL below.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA57.td:419
+// ASIMD shift by register, basic, D-form
+def : InstRW<[A57Write_3cyc_1X_NonMul_Forward], (instregex "^[SU]SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
 
----------------
mnadeem wrote:
> dmgreen wrote:
> > What is a ^[SU]SHLv1i8 ?
> > Same for all these others.
> SSHL and USHL D-form. 
> 
> https://godbolt.org/z/a7jo7a 
> The schedule was missing. These should only use the X Unit but seem to be using Units X/W
> 
This can drop the v1iX (except i64). These are all the valid SSHL instructions, the bottom ones being the important ones.
```
SSHLLB_ZZI_D        = 4444,
SSHLLB_ZZI_H        = 4445,
SSHLLB_ZZI_S        = 4446,
SSHLLT_ZZI_D        = 4447,
SSHLLT_ZZI_H        = 4448,
SSHLLT_ZZI_S        = 4449,
SSHLLv16i8_shift    = 4450,
SSHLLv2i32_shift    = 4451,
SSHLLv4i16_shift    = 4452,
SSHLLv4i32_shift    = 4453,
SSHLLv8i16_shift    = 4454,
SSHLLv8i8_shift     = 4455,
SSHLv16i8   = 4456,        
SSHLv1i64   = 4457,        
SSHLv2i32   = 4458,        
SSHLv2i64   = 4459,        
SSHLv4i16   = 4460,        
SSHLv4i32   = 4461,        
SSHLv8i16   = 4462,        
SSHLv8i8    = 4463,        
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92296/new/

https://reviews.llvm.org/D92296