[PATCH] D93229: [VectorCombine] allow peeking through GEPs when creating a vector load

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: llvm/test/Transforms/VectorCombine/X86/load.ll:276
+; AVX2-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 2
+; AVX2-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX2-NEXT:    ret <8 x i16> [[R]]
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Note that the SSE2 cost model is conservatively giving:
      {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
                                                  // + pshufd/unpck

...so that's why we do not vectorize the tests here.


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  https://reviews.llvm.org/D93229/new/

https://reviews.llvm.org/D93229