[PATCH] D92405: [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 14 06:34:31 PST 2020
arsenm added inline comments.
================
Comment at: llvm/lib/CodeGen/LiveIntervals.cpp:705-706
- // Keep track of subregister ranges.
- SmallVector<std::pair<const LiveInterval::SubRange*,
- LiveRange::const_iterator>, 4> SRs;
----------------
What was the point of copying out the subranges here before?
================
Comment at: llvm/lib/CodeGen/LiveIntervals.cpp:728-750
+ SlotIndex InstrSI = RI->end;
// A block index indicates an MBB edge.
- if (RI->end.isBlock())
+ if (InstrSI.isBlock())
continue;
- MachineInstr *MI = getInstructionFromIndex(RI->end);
+ MachineInstr *MI = getInstructionFromIndex(InstrSI);
if (!MI)
continue;
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This looks like a separate NFC change
================
Comment at: llvm/lib/CodeGen/LiveIntervals.cpp:794-795
+ if (MO.getSubReg() == 0)
+ if (const TargetRegisterClass *TRC = MRI->getRegClassOrNull(Reg))
+ UseMask = TRC->getLaneMask();
if ((UseMask & ~DefinedLanesMask).any())
----------------
getRegClass should be sufficient. There can't be a vreg without a class at this point
================
Comment at: llvm/test/CodeGen/PowerPC/subreg-killed.mir:31-101
+name: test
+alignment: 16
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
----------------
Should be able to drop most if not all of this
================
Comment at: llvm/test/CodeGen/PowerPC/subreg-killed.mir:110-132
+ undef %14.sub_vsx1:vsrprc_with_sub_64_in_vfrc = COPY $v5
+ %14.sub_vsx0:vsrprc_with_sub_64_in_vfrc = COPY $v4
+ undef %8.sub_vsx1:vsrprc_with_sub_64_in_vfrc = COPY $v3
+ %8.sub_vsx0:vsrprc_with_sub_64_in_vfrc = COPY $v2
+ %4:g8rc_and_g8rc_nox0 = LD 0, %fixed-stack.0 :: (load 8 from %fixed-stack.0, align 16)
+ %8:vsrprc_with_sub_64_in_vfrc = KILL_PAIR %8
+ undef %15.sub_pair0:uaccrc = COPY %8
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Can you simplify this at all? -run-pass=none after deleting the register section will also compact these vreg numbers
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D92405/new/
https://reviews.llvm.org/D92405
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