[PATCH] D93212: [VE] Correct addRegisterClass calls

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added a subscriber: hiraditya.
kaz7 requested review of this revision.
Herald added a subscriber: llvm-commits.

Correct addRegisterClass calls for vector mask registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93212

Files:
  llvm/lib/Target/VE/VEISelLowering.cpp


Index: llvm/lib/Target/VE/VEISelLowering.cpp
===================================================================
--- llvm/lib/Target/VE/VEISelLowering.cpp
+++ llvm/lib/Target/VE/VEISelLowering.cpp
@@ -73,8 +73,6 @@
 static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64,
                                    MVT::v256f32, MVT::v512f32, MVT::v256f64};
 
-static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
-
 void VETargetLowering::initRegisterClasses() {
   // Set up the register classes.
   addRegisterClass(MVT::i32, &VE::I32RegClass);
@@ -86,8 +84,8 @@
   if (Subtarget->enableVPU()) {
     for (MVT VecVT : AllVectorVTs)
       addRegisterClass(VecVT, &VE::V64RegClass);
-    for (MVT MaskVT : AllMaskVTs)
-      addRegisterClass(MaskVT, &VE::VMRegClass);
+    addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+    addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
   }
 }
 


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