[PATCH] D93067: [AMDGPU] Use multi-dword flat scratch for spilling

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:750
+                                          unsigned EltSize,
+                                          const SIInstrInfo *TII) {
+  bool IsStore = TII->get(LoadStoreOp).mayStore();
----------------
Move TII to first parameter since it behaves like this


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:923
+      Register Sub = IsSubReg
+             ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
+             : ValueReg;
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Register constructor should be unnecessary?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:944
 
-    if (!MIB.getInstr()) {
-      unsigned FinalReg = SubReg;
+    unsigned RemRegOffset = Lane * 4;
+    unsigned RemEltSize = EltSize - (RemRegOffset - RegOffset);
----------------
Comment what this offset is


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93067/new/

https://reviews.llvm.org/D93067