[llvm] fa31f33 - [X86] Add isel patterns to form VPDPWSSD from (add (vpmaddwd X, Y), Z) when AVXVNNI is enabled.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 13 12:02:29 PST 2020
Author: Craig Topper
Date: 2020-12-13T12:02:07-08:00
New Revision: fa31f337a259acac1731571146d5734208c616d0
URL: https://github.com/llvm/llvm-project/commit/fa31f337a259acac1731571146d5734208c616d0
DIFF: https://github.com/llvm/llvm-project/commit/fa31f337a259acac1731571146d5734208c616d0.diff
LOG: [X86] Add isel patterns to form VPDPWSSD from (add (vpmaddwd X, Y), Z) when AVXVNNI is enabled.
We already have these patterns for AVX512VNNI.
Added:
llvm/test/CodeGen/X86/avxvnni.ll
Modified:
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/test/CodeGen/X86/avx512vnni.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index f223a152fff6..d250fd9ad44c 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -11914,11 +11914,6 @@ defm VPDPBUSDS : VNNI_common<0x51, "vpdpbusds", X86Vpdpbusds, SchedWriteVecIMul
defm VPDPWSSD : VNNI_common<0x52, "vpdpwssd", X86Vpdpwssd, SchedWriteVecIMul, 1>;
defm VPDPWSSDS : VNNI_common<0x53, "vpdpwssds", X86Vpdpwssds, SchedWriteVecIMul, 1>;
-def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
- (X86vpmaddwd node:$lhs, node:$rhs), [{
- return N->hasOneUse();
-}]>;
-
// Patterns to match VPDPWSSD from existing instructions/intrinsics.
let Predicates = [HasVNNI] in {
def : Pat<(v16i32 (add VR512:$src1,
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 36dd5cbe9e5f..896a2fa58f72 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7206,6 +7206,26 @@ defm VPDPBUSDS : avx_vnni_rm<0x51, "vpdpbusds", X86Vpdpbusds, 0>, ExplicitVEXPr
defm VPDPWSSD : avx_vnni_rm<0x52, "vpdpwssd", X86Vpdpwssd, 1>, ExplicitVEXPrefix;
defm VPDPWSSDS : avx_vnni_rm<0x53, "vpdpwssds", X86Vpdpwssds, 1>, ExplicitVEXPrefix;
+def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs),
+ (X86vpmaddwd node:$lhs, node:$rhs), [{
+ return N->hasOneUse();
+}]>;
+
+let Predicates = [HasAVXVNNI, NoVLX_Or_NoVNNI] in {
+ def : Pat<(v8i32 (add VR256:$src1,
+ (X86vpmaddwd_su VR256:$src2, VR256:$src3))),
+ (VPDPWSSDYrr VR256:$src1, VR256:$src2, VR256:$src3)>;
+ def : Pat<(v8i32 (add VR256:$src1,
+ (X86vpmaddwd_su VR256:$src2, (load addr:$src3)))),
+ (VPDPWSSDYrm VR256:$src1, VR256:$src2, addr:$src3)>;
+ def : Pat<(v4i32 (add VR128:$src1,
+ (X86vpmaddwd_su VR128:$src2, VR128:$src3))),
+ (VPDPWSSDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
+ def : Pat<(v4i32 (add VR128:$src1,
+ (X86vpmaddwd_su VR128:$src2, (load addr:$src3)))),
+ (VPDPWSSDrm VR128:$src1, VR128:$src2, addr:$src3)>;
+}
+
//===----------------------------------------------------------------------===//
// VPERMIL - Permute Single and Double Floating-Point Values
//
diff --git a/llvm/test/CodeGen/X86/avx512vnni.ll b/llvm/test/CodeGen/X86/avx512vnni.ll
index 2464a3e93ac6..7dde6451074a 100644
--- a/llvm/test/CodeGen/X86/avx512vnni.ll
+++ b/llvm/test/CodeGen/X86/avx512vnni.ll
@@ -1,134 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
-; CHECK-NEXT: retq
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %1, %a0
- ret <4 x i32> %2
-}
-
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
-; CHECK-NEXT: retq
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %a0, %1
- ret <4 x i32> %2
-}
-
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
-; CHECK-NEXT: retq
- %a1 = load <8 x i16>, <8 x i16>* %p1
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %1, %a0
- ret <4 x i32> %2
-}
-
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_load2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
-; CHECK-NEXT: retq
- %a2 = load <8 x i16>, <8 x i16>* %p2
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %1, %a0
- ret <4 x i32> %2
-}
-
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
-; CHECK-NEXT: retq
- %a1 = load <8 x i16>, <8 x i16>* %p1
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %a0, %1
- ret <4 x i32> %2
-}
-
-define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
-; CHECK-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
-; CHECK-NEXT: retq
- %a2 = load <8 x i16>, <8 x i16>* %p2
- %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
- %2 = add <4 x i32> %a0, %1
- ret <4 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
-; CHECK-NEXT: retq
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %1, %a0
- ret <8 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
-; CHECK-NEXT: retq
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %a0, %1
- ret <8 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
-; CHECK-NEXT: retq
- %a1 = load <16 x i16>, <16 x i16>* %p1
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %1, %a0
- ret <8 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_load2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
-; CHECK-NEXT: retq
- %a2 = load <16 x i16>, <16 x i16>* %p2
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %1, %a0
- ret <8 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
-; CHECK-NEXT: retq
- %a1 = load <16 x i16>, <16 x i16>* %p1
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %a0, %1
- ret <8 x i32> %2
-}
-
-define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
-; CHECK-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
-; CHECK-NEXT: retq
- %a2 = load <16 x i16>, <16 x i16>* %p2
- %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
- %2 = add <8 x i32> %a0, %1
- ret <8 x i32> %2
-}
-
define <16 x i32> @test_pmaddwd_v32i16_add_v16i32(<16 x i32> %a0, <32 x i16> %a1, <32 x i16> %a2) {
; CHECK-LABEL: test_pmaddwd_v32i16_add_v16i32:
; CHECK: # %bb.0:
@@ -193,6 +65,4 @@ define <16 x i32> @test_pmaddwd_v32i16_add_v16i32_commute_load2(<16 x i32> %a0,
ret <16 x i32> %2
}
-declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>)
-declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>)
declare <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16>, <32 x i16>)
diff --git a/llvm/test/CodeGen/X86/avxvnni.ll b/llvm/test/CodeGen/X86/avxvnni.ll
new file mode 100644
index 000000000000..ff7fd9fc5cc5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avxvnni.ll
@@ -0,0 +1,195 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avxvnni | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+avx512bw,+avxvnni | FileCheck %s --check-prefixes=CHECK,AVX
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd %xmm2, %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %1, %a0
+ ret <4 x i32> %2
+}
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute(<4 x i32> %a0, <8 x i16> %a1, <8 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32_commute:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd %xmm2, %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32_commute:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %a0, %1
+ ret <4 x i32> %2
+}
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32_load1:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32_load1:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %a1 = load <8 x i16>, <8 x i16>* %p1
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %1, %a0
+ ret <4 x i32> %2
+}
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32_load2:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32_load2:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %a2 = load <8 x i16>, <8 x i16>* %p2
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %1, %a0
+ ret <4 x i32> %2
+}
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load1(<4 x i32> %a0, <8 x i16>* %p1, <8 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load1:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load1:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %a1 = load <8 x i16>, <8 x i16>* %p1
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %a0, %1
+ ret <4 x i32> %2
+}
+
+define <4 x i32> @test_pmaddwd_v8i16_add_v4i32_commute_load2(<4 x i32> %a0, <8 x i16> %a1, <8 x i16>* %p2) {
+; AVX-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load2:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v8i16_add_v4i32_commute_load2:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %xmm1, %xmm0
+; AVX512-NEXT: retq
+ %a2 = load <8 x i16>, <8 x i16>* %p2
+ %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a1, <8 x i16> %a2)
+ %2 = add <4 x i32> %a0, %1
+ ret <4 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd %ymm2, %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %1, %a0
+ ret <8 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute(<8 x i32> %a0, <16 x i16> %a1, <16 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32_commute:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd %ymm2, %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32_commute:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %a0, %1
+ ret <8 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32_load1:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32_load1:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %a1 = load <16 x i16>, <16 x i16>* %p1
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %1, %a0
+ ret <8 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32_load2:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32_load2:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %a2 = load <16 x i16>, <16 x i16>* %p2
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %1, %a0
+ ret <8 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load1(<8 x i32> %a0, <16 x i16>* %p1, <16 x i16> %a2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load1:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load1:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %a1 = load <16 x i16>, <16 x i16>* %p1
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %a0, %1
+ ret <8 x i32> %2
+}
+
+define <8 x i32> @test_pmaddwd_v16i16_add_v8i32_commute_load2(<8 x i32> %a0, <16 x i16> %a1, <16 x i16>* %p2) {
+; AVX-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load2:
+; AVX: # %bb.0:
+; AVX-NEXT: {vex} vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_pmaddwd_v16i16_add_v8i32_commute_load2:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpdpwssd (%rdi), %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %a2 = load <16 x i16>, <16 x i16>* %p2
+ %1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a1, <16 x i16> %a2)
+ %2 = add <8 x i32> %a0, %1
+ ret <8 x i32> %2
+}
+
+declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>)
+declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>)
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