[PATCH] D93093: [VE] Add logical mask intrinsic instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 added a comment.

Hmm, not sure why it needs.  These new tests shows the correctness of code modifications enough, IMO.



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Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:87-89
+    addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+    addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
   }
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simoll wrote:
> Can we make this a separate patch?
I condider that, but it's difficult to do so.  In order to do so, a regression test is required.  Making such a regression test requires additional implementation of vector mask register copy function.  I'm not sure what is required to implement that.

Probablly, I should ask them when you add above code.  I asked tests for V64 registers but forgot to ask tests of VM registers.

Anywa, this time I add new intrinsic instructions supporting vm512 and hit this bug.  You can see crashes by disabling above modifications and run new regression tests that this patch adds.  Then, you can see no crash after enabling above modifications and run the identical tests again.  Isn't that enough?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93093/new/

https://reviews.llvm.org/D93093