[PATCH] D93161: [VE] Support atomic exchange instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: jfb, hiraditya.
kaz7 requested review of this revision.
Herald added a subscriber: llvm-commits.

Support atomic exchange and atomic compare and exchange instructions.
Change CAS and TS1AM instructions for ISel patterns.  Add selectADDRzi
pattern for them.  Add TS1AM pseudo instruction also for better ISel.
Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw
instructions except atomicrmw xchg.  Add custom lower for i8/i16
atomicrmw xchg.  Modify replaceFI to support CAS/TS1AM instructions
which use "reg+disp" operands instead of "reg+imm+disp" operands.
And, add several regression tests to check the correctness.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93161

Files:
  llvm/lib/Target/VE/VEISelDAGToDAG.cpp
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/VE/VEISelLowering.h
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/lib/Target/VE/VERegisterInfo.cpp
  llvm/test/CodeGen/VE/Scalar/atomic.ll
  llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
  llvm/test/CodeGen/VE/Scalar/atomic_load.ll
  llvm/test/CodeGen/VE/Scalar/atomic_store.ll
  llvm/test/CodeGen/VE/Scalar/atomic_swap.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D93161.311384.patch
Type: text/x-patch
Size: 244408 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201212/cd81adb6/attachment-0001.bin>