[PATCH] D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:337
+    // RVV intrinsics may have illegal operands.
+    for (auto VT : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
+      setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
----------------
evandro wrote:
> craig.topper wrote:
> > Is MVT::i1 needed here? The custom lowering only checks i8/i16/i32.
> > 
> > Should we only have i32 as custom with RV64?
> Good question...
MVT::i1 is not needed. We need i8/i16. In vadd.vx, the SEW of scalar argument may be 8 or 16.


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  https://reviews.llvm.org/D93013/new/

https://reviews.llvm.org/D93013