[PATCH] D92479: [RISCV] remove redundant instruction when eliminate frame index

luxufan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 11 04:52:44 PST 2020


StephenFan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:174
     TII->movImm(MBB, II, DL, ScratchReg, Offset);
+    if (MI.getOpcode() == RISCV::ADDI) {
+      BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
----------------
kito-cheng wrote:
> Just curios, does it possible get any other opcode than ADDI? below code are just update `Offset`, I guess that means we already assume it must be ADDI here? But I could be wrong since I didn't seriously tracing here before.
> 
> If my assumption is right then the code could be further simplified?  
The ADDI is generated when the frameindexSDNode be selected to ADDI

```
  case ISD::FrameIndex: {
    SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
    SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
    ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
    return;
  }
```
In the eliminateFrameIndex function, I think the instructions that contains the frameindex operand are
ADDI (show above) and load/store instruction that come from loadRegFromStackSlot and storeRegToStackSlot function. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92479/new/

https://reviews.llvm.org/D92479



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