[PATCH] D93093: [VE] Add logical vector intrinsic instructions

[Simon Moll via Phabricator via llvm-commits]

simoll added a comment.

Just this one thing, else, LGTM.



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Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:87-89
+    addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+    addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
   }
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Can we make this a separate patch?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93093/new/

https://reviews.llvm.org/D93093