[PATCH] D93099: [PowerPC] Select the D-Form load if we know its offset meets the requirement

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: hfinkel, nemanjai, shchenz, PowerPC.
Herald added subscribers: kbarton, hiraditya.
steven.zhang requested review of this revision.
Herald added a project: LLVM.

I happens to see this issue and this is a simple patch to fix the issue I saw.

The LD/STD likewise instruction are selected only when the alignment in the load/store >= 4 to deal with the case that the offset might not be known(i.e. relocations), which is done by this patch.

  commit b09680b0f793254c7985dd42f3ef8ea56a388c10
  Author: Hal Finkel <hfinkel at anl.gov>
  Date:   Mon Mar 18 23:00:58 2013 +0000
  
      Fix PPC unaligned 64-bit loads and stores
  
      PPC64 supports unaligned loads and stores of 64-bit values, but
      in order to use the r+i forms, the offset must be a multiple of 4.
      Unfortunately, this cannot always be determined by examining the
      immediate itself because it might be available only via a TOC entry.
  
      In order to get around this issue, we additionally predicate the
      selection of the r+i form on the alignment of the load or store
      (forcing it to be at least 4 in order to select the r+i form).

That means we have to select the X-Form load for `%0 = load i64, i64* %arrayidx, align 2` In fact, we can still select the D-Form load if the offset is known. So, we only query the load/store alignment when we don't know if the offset is a multiple of 4.

Though we have the peephole to transform the X-Form load/store to D-Form load/store, and that's why we didn't see too much assembly changed. But it exposes more opportunities for us if we can select it as D-Form as early as possible as some optimization only works for D-Form load.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93099

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/ldst-align.ll
  llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
  llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
  llvm/test/CodeGen/PowerPC/pr45186.ll
  llvm/test/CodeGen/PowerPC/store-combine.ll
  llvm/test/CodeGen/PowerPC/unal4-std.ll
  llvm/test/CodeGen/PowerPC/unaligned.ll

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