[PATCH] D92089: [PowerPC] Materialize i64 constants by enumerated patterns.

[EsmeYi via Phabricator via llvm-commits]

Esme added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:899
+  // after rotation.
+  if ((LZ + FO + TO) > 48) {
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
----------------
stefanp wrote:
> One more question: Isn't this the pattern above just a subset of this one?
> 
> ```
> if ((LZ + TO) > 48) {
>  ...
> }
> 
> if ((LZ + FO + TO) > 48) {
>   ...
> }
> ```
> They both use only two instructions to materialize the constant. If you delete the first one the second one will also catch all of those cases and be the same number of instructions.
> One more question: Isn't this the pattern above just a subset of this one?
> 
> ```
> if ((LZ + TO) > 48) {
>  ...
> }
> 
> if ((LZ + FO + TO) > 48) {
>   ...
> }
> ```
> They both use only two instructions to materialize the constant. If you delete the first one the second one will also catch all of those cases and be the same number of instructions.

They are similar but different :D  The patterns are very tricky indeed. Hope the following sketches can make you clear.
First one (LZ + TO) > 48
```
  // +--LZ--||-15-bit-||--TO--+     +-------------|--16-bit--+
  // |00000001bbbbbbbbb1111111| ->  |00000000000001bbbbbbbbb1|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  //          Imm                   (Imm >> (48 - LZ) & 0xffff)
  // +----sext-----|--16-bit--+     +clear-|-----------------+
  // |11111111111111bbbbbbbbb1| ->  |00000001bbbbbbbbb1111111|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  // LI8 : sext many leading zeros   RLDICL : rotate left (48 - LZ), clear left LZ
```
Second one (LZ + FO + TO) > 48 (I will add this in next update)
```
  // +-LZ-FO||-15-bit-||--TO--+     +-------------|--16-bit--+
  // |00011110bbbbbbbbb1111111| ->  |000000000011110bbbbbbbbb|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  //            Imm                    (Imm >> TO) & 0xffff
  // +----sext-----|--16-bit--+     +LZ|---------------------+
  // |111111111111110bbbbbbbbb| ->  |00011110bbbbbbbbb1111111|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  // LI8 : sext many leading zeros   RLDICL : rotate left TO, clear left LZ
```
Assume we use the second pattern to handle the first case :
```
  // +--LZ--||-15-bit-||--TO--+     +--------------|-15-bit--+
  // |00000001bbbbbbbbb1111111| ->  |000000000000001bbbbbbbbb|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  //         Imm                       (Imm >> TO) & 0xffff)
  // +----sext------|-15-bit--+     +------------------------+
  // |000000000000001bbbbbbbbb| ->  |00000001bbbbbbbbb0000000|
  // +------------------------+     +------------------------+
  // 63                      0      63                      0
  // LI : no leading ones             incorrect result :(
```


Repository:
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  https://reviews.llvm.org/D92089/new/

https://reviews.llvm.org/D92089