[PATCH] D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:28
+      if (C->isNullValue()) {
+        return SDValue(CurDAG->getMachineNode(RISCV::ADDI, DL, MVT::i64,
+                       CurDAG->getRegister(RISCV::X0, MVT::i64),
----------------
`Subtarget->XLenVT()` instead of `MVT::i64`, here and below, yes?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:20
+//--------------------------------------------
+// !X0 |  X0 |          ~0 | Set vl to VLMAX
+//  X0 |  X0 | Value in vl | Keep existing vl
----------------
```
s/~0/VLMAX/
```


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:21
+// !X0 |  X0 |          ~0 | Set vl to VLMAX
+//  X0 |  X0 | Value in vl | Keep existing vl
+def NoX0 : SDNodeXForm<undef,
----------------
"Keep current `vl`, just change `vtype`"


Repository:
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  https://reviews.llvm.org/D93013/new/

https://reviews.llvm.org/D93013