[PATCH] D93080: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The compiler is making no effort to preserve upper elements. To do so would require another source operand tied with the destination and a different intrinsic interface to give control of this source to the programmer.

This patch changes the tail policy to agnostic so that the CPU doesn't need to make an effort to preserve them.


https://reviews.llvm.org/D93080

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
  llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll

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