[PATCH] D93006: [RISCV] Initial support for RVV intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Are you proposing to do custom isel in RISCVISelDAGToDAG.cpp using lookupPseudoByIntrinsicAndLMUL and not using the RISCVGenDAGISel.inc table? Do you have an implementation of that yet?



================
Comment at: llvm/test/CodeGen/RISCV/rvv/intrinsic-load-add-store-32.ll:10
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vle32.v v25, (a1)
----------------
This is setting the VL to VLmax which isn't what the spec wants. It should get the value from the previous vsetvl intrinsic or maybe the previous intrinsic that had a vl argument.

Our internal implementation has been implementing the intrinsics without vl by inserting a readvl intrinsic and a call to the intrisics that take vl. But we've been finding issues with this. The readvl is acting as an optimization barrier. It also doesn't have any ordering in IR with respect to intrinsics that have a vl argument unless we mark all intrinsics has having side effects.

What are your thoughts on this?


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