[llvm] e4a23a4 - [Tablegen] Use llvm::is_contained (NFC)

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2020-12-09T23:34:07-08:00
New Revision: e4a23a418b4ca007e2c6c0bf488073cbc5f81290

URL: https://github.com/llvm/llvm-project/commit/e4a23a418b4ca007e2c6c0bf488073cbc5f81290
DIFF: https://github.com/llvm/llvm-project/commit/e4a23a418b4ca007e2c6c0bf488073cbc5f81290.diff

LOG: [Tablegen] Use llvm::is_contained (NFC)

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenSchedule.cpp
    llvm/utils/TableGen/CodeGenTarget.cpp
    llvm/utils/TableGen/RegisterBankEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 49a7575dce95..f1bfe42001a3 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -950,9 +950,9 @@ void CodeGenSchedModels::collectSchedClasses() {
     }
     // If ProcIndices contains zero, the class applies to all processors.
     LLVM_DEBUG({
-      if (!std::count(ProcIndices.begin(), ProcIndices.end(), 0)) {
+      if (!llvm::is_contained(ProcIndices, 0)) {
         for (const CodeGenProcModel &PM : ProcModels) {
-          if (!std::count(ProcIndices.begin(), ProcIndices.end(), PM.Index))
+          if (!llvm::is_contained(ProcIndices, PM.Index))
             dbgs() << "No machine model for " << Inst->TheDef->getName()
                    << " on processor " << PM.ModelName << '\n';
         }
@@ -1248,7 +1248,7 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
     bool HasMatch = false;
     for (const Record *Rec : PM.ItinRWDefs) {
       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");
-      if (!std::count(Matched.begin(), Matched.end(), ItinClassDef))
+      if (!llvm::is_contained(Matched, ItinClassDef))
         continue;
       if (HasMatch)
         PrintFatalError(Rec->getLoc(), "Duplicate itinerary class "
@@ -1767,7 +1767,7 @@ void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites,
   LLVM_DEBUG(dbgs() << '\n');
 
   LastTransitions = makePerProcessorTransitions(
-      LastTransitions[0], llvm::count(ProcIndices, 0)
+      LastTransitions[0], llvm::is_contained(ProcIndices, 0)
                               ? ArrayRef<unsigned>(getAllProcIndices())
                               : ProcIndices);
   // Collect all PredTransitions for individual operands.
@@ -2046,7 +2046,7 @@ void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
     for (RecIter II = PM.ItinRWDefs.begin(), IE = PM.ItinRWDefs.end();
          II != IE; ++II) {
       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
-      if (!std::count(Matched.begin(), Matched.end(), ItinClassDef))
+      if (!llvm::is_contained(Matched, ItinClassDef))
         continue;
       if (HasMatch)
         PrintFatalError((*II)->getLoc(), "Duplicate itinerary class "

diff  --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index d8e1d7f8cf0d..61b9fa853198 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -356,10 +356,7 @@ CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
       continue;
 
     // We have a class. Check if it supports this value type.
-    if (llvm::none_of(SubClassWithSubReg->VTs,
-                      [&ValueTy](const ValueTypeByHwMode &ClassVT) {
-                        return ClassVT == ValueTy;
-                      }))
+    if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
       continue;
 
     // We have a register class which supports both the value type and

diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index e7583f7b4b51..6a45213e1d66 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -71,10 +71,7 @@ class RegisterBank {
 
   /// Add a register class to the bank without duplicates.
   void addRegisterClass(const CodeGenRegisterClass *RC) {
-    if (std::find_if(RCs.begin(), RCs.end(),
-                     [&RC](const CodeGenRegisterClass *X) {
-                       return X == RC;
-                     }) != RCs.end())
+    if (llvm::is_contained(RCs, RC))
       return;
 
     // FIXME? We really want the register size rather than the spill size