[PATCH] D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR

Wed Dec 9 03:27:23 PST 2020

paulwalker-arm added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/split-vector-insert.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -mtriple=aarch64-- -mcpu=a64fx -debug-only=legalize-types 2>&1 | FileCheck %s --check-prefix=CHECK-LEGALIZATION
+; RUN: llc < %s -o - -mtriple=aarch64-- -mcpu=a64fx | FileCheck %s --check-prefix=CHECK-CODEGEN
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This RUN line requires an asserts build so the test will need `; REQUIRES: asserts` .  However, for what it's worth it seems overkill to test both the code generation output and the result of the legaliser with generally the assembler output from llc usually being enough.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92760/new/

https://reviews.llvm.org/D92760