[llvm] af5fd65 - [RISCV] Fix missing def operand when creating VSETVLI pseudos

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2020-12-09T09:35:28Z
New Revision: af5fd658952a7f1d9d2a1007217755bd04b4dd4e

URL: https://github.com/llvm/llvm-project/commit/af5fd658952a7f1d9d2a1007217755bd04b4dd4e
DIFF: https://github.com/llvm/llvm-project/commit/af5fd658952a7f1d9d2a1007217755bd04b4dd4e.diff

LOG: [RISCV] Fix missing def operand when creating VSETVLI pseudos

The register operand was not being marked as a def when it should be. No tests
for this in the main branch as there are not yet any pseudos without a
non-negative VLIndex.

Also change the type of a virtual register operand from unsigned to Register
and adjust formatting.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92823

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2c2ae54dbd59..c58d44771f50 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1942,13 +1942,13 @@ static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
 
   if (VLIndex >= 0) {
     // Set VL (rs1 != X0).
-    unsigned DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+    Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     MIB.addReg(DestReg, RegState::Define | RegState::Dead)
-       .addReg(MI.getOperand(VLIndex).getReg());
+        .addReg(MI.getOperand(VLIndex).getReg());
   } else
     // With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
-    MIB.addReg(RISCV::X0, RegState::Dead)
-       .addReg(RISCV::X0, RegState::Kill);
+    MIB.addReg(RISCV::X0, RegState::Define | RegState::Dead)
+        .addReg(RISCV::X0, RegState::Kill);
 
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(Multiplier, ElementWidth,